AUDF0 = $17
Audio Frequency Divider Register 0
| WRITE | Name | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0
|
| $17 | AUDF0 | D4 | D3 | D2 | D1 | D0 |
Frequency Selection
Frequency selection is controlled by writing to a 5 bit audio frequency register (AUDF0, AUDF1). The value written is used to divide a 30 KHz reference frequency creating higher or lower pitch of whatever type of sound is created by the noise-tone generator (see AUDC0, AUDC1). By combining the pure tones available from the noise-tone generator with frequency selection a wide range of tones can be generated.
Clock pulses (at approximately 30 KHz) from the horizontal sync counter pass through a divide by N circuit which is controlled by the output code from a five bit frequency register (AUDF). This register can be loaded (written) by the microprocessor at any time, and causes the 30 KHz clocks to be divided by 1 (code 00000) through 32 (code 11111). This produces pulses that are digitally adjustable from approximately 30 KHz to 1 KHz and are used to clock the noise-tone generator.
D4 | D3 | D2 | D1 | D0 | 30 KHz divide by | ||||
0 | 0 | 0 | 0 | 0 | none | ||||
0 | 0 | 0 | 0 | 1 | 2 | ||||
0 | 0 | 0 | 0 | 0 | 3 | ||||
...
| |||||||||
1 | 1 | 1 | 0 | 1 | 30 | ||||
1 | 1 | 1 | 1 | 0 | 31 | ||||
1 | 1 | 1 | 1 | 1 | 32 | ||||
SECAM Compatibility
SECAM machines use PAL software with one exception. when a sound is to be turned off, it must be one by setting AUDV0/AUDV1 to 0, not by setting AUDC0/AUDC1 to 0. Otherwise, you get an obnoxious background sound.
Related
Related
see TIA