The PF "register" is a 20-bit wide representation of playfield pixels drawn to the screen. These 20 bits are spread across three actual registers. Left-to-right these are PF0 (4 bits), PF1 (8 bits), and PF2 (8 bits). PF0 and PF2 are drawn in right-to-left (mirrored) bit-order. Playfield pixels are low-resolution, with 40 pixels across the screen, achieved by drawing the contents of the PF register; once for the left side of the TV screen, and once for the right side of the TV screen. The right side may be mirrored through REFLCT of CTRLPF.
To achieve different pixel shapes on the left and right sides of the screen, the PF register (or rather, PF0, PF1 and PF2) must be written on-the-fly when they are not being accessed for display. The timing constraints of PF register writes are described in some detail in Playfield Timing.