I didn't have a chance to have a good look at last nights test card i filmed till now ,i can see removing the missing sync the start and end line looks to me to be in the middle of the picture ..could be a random start ..not sure .
That's an arbitrary thing Harry, there is no frame sync without the missing pulse - totally normal.
On the schematic i did do a change i am using the output of the 555 timer right to the pin 3 of the PLL ...
Harry, i have only just seen your schematic - it wasn't there when I originally read your post - but I see there is a considerable change on the right hand side in that you are not using the feedback portion of the handbooks schematic - that may be worth adding. In fact, if my understanding of the circuit is correct (strangely there has never been, to my knowledge, a real explanation of how the motor current feedback part works) then that 22 uF capacitor and the second trimmer shouldn't be there if you are not feeding back some of the motor current.
With regards to the output of the 555 going to the 4046 - that is what I had assumed you were doing and is perfectly correct.
if i out put the PLL to the video mixer instead of the 555 timers .
What would you be trying to achieve by doing that Harry? it would mean you would have a varying sync whilst it is coming up to speed, and no sync pulse at all when it was at speed. *However, you COULD use the clock output to feed the mixer - it would only be correct when the disk speed is exactly 750 RPM however.
Harry I am trying to analyse your wave files and finding some strange things that I am having difficulty explaining. Can you answer a couple of questions please?
1) with all of the files except the cat card there is not meant to be any picture right? Can you tell me was the FSS sensor picking up any light at all during the test or was it disconnected?
2) are you adjusting the speed at all during the actual recording or are you setting it first and then recording?
3) is the encoder sensor vibrating at all when running the disk?
BTW the cat example shows that the circuit IS trying to lock but is hunting around the lock point - this is a common syndrome most of us using this circuit has experienced and usually is overcome by tweaking the component values.
OTOH the others seem to be locked but at just slightly the wrong speed.
Actually it would be very useful if you could record the clock pulse stream directly (as indicated at *) so I could check it's speed.
Oh and BTW, why have you reverted to a 44.1 Khz sampling rate? It's a cow of a sample rate to use and serves no purpose unless you are going to burn to CD. 48kHz would be MUCH better. In fact ANY sampling rate at and above 20kHz and an integer multiple of 400 is MUCH better.