I wonder if an "Integrate and Dump" filter could be made to work here? With a clock used to sample the discriminator output at regular intervals (say 4151 Hz for 256 samples for a 15 Hz line to 4654 Hz for a 16.66 Hz line), the process would go as follows:
1) Integrate the raw waveform coming out of the Travis discriminator over one of these discrete 4 kHz (pixel) sampling intervals.
2) Latch the integrator's output voltage in a Sample and Hold circuit (LF398).
3) Alert the A/D converter that a new sample has arrived.
4) Reset the integrator and repeat the process over again.
Assuming this could be realized in practice, the Integrate and Dump filter would provide the optimum amount of filtering for your specified sampling rate. Furthermore, it operates completely in the time domain, so
it can't ring or overshoot! Each and every pixel gets filtered independently of one another, without any chance of overlap or crosstalk between them.
Here is an analog representation of this process applied to the processing of digital signals. Note that this illustration is deceptive in that the Integrator and the Sample and Hold are
not commanded simultaneously -- the output sample is latched very briefly
before the integrator is reset:
The "dump switch" that resets the integrator after each sample is latched could be one section of a 4066 CMOS switch (or all 4 section tied in parallel if they're not needed elsewhere):
- int+dump.png (42.56 KiB) Viewed 7023 times
Of course this could all be done in software by running the A/D converter at perhaps 10 or 20x the 4 kHz sampling rate, feeding the result into an accumulator after each sample, storing the result for processing/storage/display, and then resetting the accumulator and repeating the process.
But if you can't, at least the analog hardware is cheap.
73 de John, KD2BD